1. Field of the Invention
The present invention is related to Integrated Circuit (IC) chips and more particularly to providing body bias to Field Effect Transistors (FETs) in CMOS IC chips.
2. Background Description
Bulk silicon field effect transistors (FETs) are formed on the surface of a silicon chip or wafer. In the insulated gate FET technology typically referred to as CMOS, the silicon wafer or substrate may be of one conduction type, e.g., P-type, and areas or wells of a second conduction type, e.g., N-type, are formed in the P-type wafer. N-type FETs (NFETs) are formed on the surface of the P-type wafer and P-type FETs (PFETs) are formed on the surface of the N-wells. A first bias voltage, typically zero volts (0.0V) or ground (GND), is applied to the substrate to bias the NFETs and a second bias voltage, typically the supply voltage (Vhi), is applied to the N-wells. The substrate and N-well bias voltages help to stabilize respective FET electrical characteristics, including improving threshold voltage (VT) and device current stability. Changing a device bias changes device characteristics, increasing/decreasing device VT and decreasing/increasing device operating current, depending upon the magnitude and direction of the respective change. Performance improvements for these prior art bulk transistor technologies has been achieved, normally, by reducing feature size or “scaling.”
Transistor and circuit performance improvements have also come from the movement to silicon on insulator (SOI) where separate FETs are formed in a surface silicon layer. However, typically, SOI FETs are unbiased and so, suffer from what are known as body effects and history effects.
FIG. 1A shows a cross section of a prior art SOI wafer through a single FET 52 that may be an NFET or a PFET. The FET 52 is formed in a thin silicon surface layer 54 that is isolated from an underlying silicon substrate 56 by a buried oxide (BOX) layer 58. In a typically complex series of mask steps, SOI islands 60 are formed by etching shallow trenches through the surface layer 54 and filling the shallow trenches with oxide 50 to isolate islands (e.g., 60) from each other. This type of isolation is normally referred to as Shallow trench isolation (STI). STI is used to isolate circuits formed on the islands from each other and, also, isolate the FETs forming the circuits from each other. A gate oxide layer 62 is formed on the surface of the silicon islands 60. Gates 64 are patterned and formed at the device locations. Source/drain regions 66 are defined using standard implant and diffusion steps, e.g., after forming lightly doped diffusion regions (not shown) or with source drain extensions (not shown) at the gate boundaries, if desired. With each device 52, whether NFET or PFET, the source/drain regions 66 in the silicon body form an inherent lateral bipolar transistor, i.e., PNP or NPN, respectively. Once the source drain regions are formed, metal contacts (not shown) are selectively formed at source/drain regions 66 for wiring circuits together and to each other.
Ideally, the thin silicon surface layer 54 is no thicker than what is necessary to form a channel 68 between a pair of source/drain diffusions 66. In practice however, the silicon surface layer 54 is thicker than the depth of the FET's channel layer 68 and, as shown in this example, thicker than device source/drain diffusions 66. Charge stored in the un-inverted layer 70 beneath channel layer 68 of an on FET can act to lower FET threshold, causing device leakage when the device is turned off, e.g., sub-threshold leakage. Further, lowering a device's threshold changes the device's operating characteristics, e.g., making it harder to turn the device off. Charge may accumulate, for example, in an on device located between two off devices, e.g., NFETs in a three way NAND gate. A logic gate with devices that have unintentionally lowered thresholds from stored charge may sporadically operate faster than normal, i.e., when no charge is stored. Thus, a particular path may manifest sporadic race conditions from that stored charge. What is known as partially depleted SOI (PD-SOI) has provided one solution to charge trapping. PD-SOI devices have both lower device junction capacitance and exhibit significantly less dynamic threshold sensitivity to elevated body potential.
FIG. 1B shows an example of the effect of body bias on the I-V curve for a typical state of the art NFET. This example compares having the body is tied to ground 80 or to the source of the device; tide to a positive bias voltage (e.g., 0.6V) 82 slightly below the PN junction turn on voltage; and tied to the gate 84. Grounding the body 80 provides an asymmetric effect with fixed bias conditions in one direction and unfavorably variable in the other. While for some applications, e.g., an inverter or other basic logic gate, this asymmetric characteristic 80 may be beneficial, it is not for others, e.g., for pass gates where balanced operation is desired. Similarly, biasing the body slightly below turn on 82 may be advantageous, e.g., for power device applications, the sub-threshold current can cause unacceptable static or DC power. With the device tied gate to body 84, effectively dynamically biases the device to provide a much crisper characteristic with low sub-threshold current below the 0.2V threshold approaching the body to source bias 80 but with a substantially constant current above, approaching the body to positive bias voltage 84.
By contrast, the device's history of a floating body device may cause the gate to body bias vary much worse than either of the extremes 80, 82, during normal circuit operation. For example, as a floating body device is switched on and off, charged device capacitances may couple the body up or down. As result, logic switching speeds may depend on device history, with a steady state off device slowing a particular logic stage as much as 20-30% in one cycle over another, i.e., where the same device is only in an off state, transitionally. A pass gate multiplexor (Mux), for example, with several parallel such off devices may be especially sensitive to this floating body effect bipolar switching current and, therefore, may suffer random slow propagation delays. Multi stage latches or registers, e.g., pipeline registers, with pass gate coupling between stages may sit in the same state for several cycles with a high at both sides of the pass gates. Where clock gating techniques are used to power down/pause chip sections may well allow body effects to manifest in the registers, slowing reactivation. Memory arrays and static random access memories (SRAMs) in particular may have occasional long accesses from the floating body effects, when a number of cells in the same column or bit line are set the same. Under some floating body conditions, the bipolar current from other cells sharing the same bit lines as half selected SRAM cells (i.e., cells on a selected word line but in unselected columns) may inadvertently switch the half selected cells. These floating body effects pose serious design problems for densely packed SOI circuits such as for example, memory arrays. Intermittent problems may arise, such as an occasional critical path failure, spuriously reading the wrong data or, random cell failures. These types of intermittent problems are notoriously difficult to identify and diagnose. So, floating body effects cause device and circuit non-uniformities that result in difficult to identify sporadic chip failures, sometimes characterized as “soft failures.”
Consequently, a number of approaches have been used to bias device bodies and in particular to tie devices body to source (equivalent to) or gate. Unfortunately, prior art approaches have required enlarged shapes for form body contacts and, in some cases, extra device contacts. These enlarged shapes have increased device capacitances, i.e., gate to source-drain diffusion, and/or diffusion to body capacitances.
Thus, there is a need to reduce circuit sensitivity to floating body effects and in particular, to bias devices by tying the device body to a bias without large appurtenant structures that increase device capacitances.